hanbit hm d16m32m8g url: www.hbe.co.kr hanbit electronics co.,ltd. rev. 1.0 (august. 2002) 1 general description the HMD16M32M8G is a 16mbit x 32 dynamic ram high - density memory module. the module consists of eight cmos 16m x 4bit drams in 32 - pin tsopii packages mounted on a 72 - pin, double - sided, fr - 4 - printed circuit board. a 0.1uf deco upling capacitor is mounted on the printed circuit board for each dram components. the module is a single in - line memory module with edge connections and is intended for mounting in to 72 - pin edge connector sockets. all module components may be powered fro m a single 5v dc power supply and all inputs and outputs are ttl - compatible. pin assignment features w HMD16M32M8G: 4k cycles/64ms refresh gold w access times : 50, 60ns w high - density 64mbyte design w single + 5v 0.5v power supply w jedec standard pinout w fp(fast page) mode operation w ttl compatible inputs and outputs w fr4 - pcb design option s marking w timing 50 n s access - 5 60 n s access - 6 w packages 72 - pin simm m performance range speed trac tcac trc - 5 50ns 13ns 90ns - 6 60ns 15ns 110ns w part identificat ion presence detect pins 50ns 60ns pd1 vss vss pd2 nc nc pd3 vss nc pd4 vss nc pin symbol pin symbol pin symbol pin symbol 1 vss 19 a10 37 nc 55 dq11 2 dq0 20 dq4 38 nc 56 dq27 3 dq16 21 dq20 39 vss 57 dq12 4 dq1 22 dq5 40 /cas0 58 dq28 5 dq17 23 dq21 4 1 /cas2 59 vcc 6 dq2 24 dq6 42 /cas3 60 dq29 7 dq18 25 dq22 43 /cas1 61 dq13 8 dq3 26 dq7 44 /ras0 62 dq30 9 dq19 27 dq23 45 nc 63 dq14 10 vcc 28 a7 46 nc 64 dq31 11 nc 29 a11 47 /w 65 dq15 12 a0 30 vcc 48 nc 66 nc 13 a1 31 a8 49 dq8 67 pd1 14 a2 32 a9 50 dq24 68 pd2 15 a3 33 nc 51 dq9 69 pd3 16 a4 34 /ras2 52 dq25 70 pd4 17 a5 35 nc 53 dq10 71 nc 18 a6 36 nc 54 dq26 72 vss 64mbyte(16mx32) 72 - pin fp mode 4k ref . simm design 5v part no. HMD16M32M8G
hanbit hm d16m32m8g url: www.hbe.co.kr hanbit electronics co.,ltd. rev. 1.0 (august. 2002) 2 functional block dia gram dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u0 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u1 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u2 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u3 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u4 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u5 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u6 dq0 cas dq1 ras dq2 oe w a0 - a11 dq3 u7 vcc vss 0.1uf or 0.22uf capacitor for each dram to all drams dq0 - dq3 dq4 - dq7 dq8 - dq11 dq12 - dq15 dq16 - dq19 dq20 - dq23 dq24 - dq27 dq28 - dq31 /cas0 /ras0 /cas1 /cas2 /cas3 /w a0 - a11 /ras2
hanbit hm d16m32m8g url: www.hbe.co.kr hanbit electronics co.,ltd. rev. 1.0 (august. 2002) 3 absolute maximum rat ings parameter symbol rating voltage on any pin relative to vss v in ,out - 1v to 7. 0v voltage on vcc supply relative to vss vcc - 1v to 7.0v power dissipation p d 6w storage temperature t stg - 55 o c to 150 o c short circuit output current i os 50ma w permanent device damage may occur if " absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc opera ting conditions ( v oltage reference to v ss , t a =0 to 70 o c ) parameter symbol min typ . max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.4 - vcc+1 v input low voltage v il - 1.0 - 0.8 v dc and operating cha racteristics symbol speed min max units - 5 - 880 ma i cc1 - 6 - 800 ma i cc2 - 16 ma - 5 - 880 ma i cc3 - 6 - 800 ma - 5 - 720 ma i cc4 - 6 - 560 ma i cc5 - 8 ma - 5 - 880 ma i cc6 - 6 - 800 ma i l(l) - 60 5 m a i o(l) - 5 5 m a v oh 2.4 - v v ol - 0.4 v
hanbit hm d16m32m8g url: www.hbe.co.kr hanbit electronics co.,ltd. rev. 1.0 (august. 2002) 4 i cc1 : operating curren t * (/ras , /cas , address cycling @t rc =min.) i cc2 : standby current ( /ras=/cas=v ih ) i cc3 : /ras only refresh current * ( /cas=v ih , /ras, address cycling @t rc =min ) i cc4 : fast page mode current * (/ras=v il , /cas, address cycling @t pc =min ) i cc5 : stand by current (/ras=/cas=vcc - 0.2v ) i cc6 : /cas - before - /ras refresh current * (/ras and /cas cycling @t rc =min ) i il : input leakage current (any input 0v v in 6.5v, all other pins not under test = 0v) i ol : output leakage current (data out is disabled, 0v v out 5.5v v oh : output high voltage level (i oh = - 5ma ) v ol : output low voltage level (i ol = 4.2ma ) * note: i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address cad be changed maximum once while /ras=v il . in i cc4 , address can be changed maximum once within one page mode cycle. capacitance ( t a =25 o c, vcc = 5v, f = 1mz ) description symbol min max units input capacitance (a0 - a11) c in1 - 40 pf input capacitance (/w) c in2 - 56 pf input capacitance (/ras0) c in3 - 58 pf input capacitance (/cas0 - /cas3) c in4 - 54 pf input/output capacitance (dq0 - 31) c dq1 - 57 pf ac characteristics ( 0 o c t a 70 o c , vcc = 5v 10%, see notes 1,2.) - 5 - 6 parameter symbol min max min max unit random read or write cycle time t rc 90 110 ns access time from /ras t rac 50 60 ns access time from /cas t cac 13 15 ns access time from column address t aa 25 30 ns /cas to output in low - z t clz 0 0 ns output buffer turn - off delay t off 0 13 0 15 ns transition time (rise and fall) t t 3 50 3 50 ns /ras precharge time t rp 30 40 ns /ras pulse width t ras 50 10k 60 10k ns /ras hold time t rsh 13 15 ns /cas hold time t csh 50 60 ns /cas pulse width t cas 13 10k 15 10k ns /ras to /cas delay time t rcd 20 37 20 45 ns /ras to column address delay time t rad 15 25 15 30 ns
hanbit hm d16m32m8g url: www.hbe.co.kr hanbit electronics co.,ltd. rev. 1.0 (august. 2002) 5 /cas to /ras precharge time t crp 5 5 ns row address set - up time t asr 0 0 ns ro w address hold time t rah 10 10 ns column address set - up time t asc 0 0 ns column address hold time t cah 10 10 ns column address hold referenced to /ras t ar 50 55 ns column address to /ras lead time t ral 25 30 ns read command set - up time t rcs 0 0 ns read command hold referenced to /cas t rch 0 0 ns read command hold referenced to /ras t rrh 0 0 ns write command hold time t wch 10 10 ns write command hold referenced to /ras t wcr 50 55 ns write command pulse width t wp 10 10 ns wr ite command to /ras lead time t rwl 13 15 ns write command to /cas lead time t cwl 13 15 ns data - in set - up time t ds 0 0 ns data - in hold time t dh 10 10 ns data - in hold referenced to /ras t dhr 50 55 ns refresh period t ref 16 16 ns write comm and set - up time t wcs 0 0 ns /cas setup time (c - b - r refresh) t csr 10 10 ns /cas hold time (c - b - r refresh) t chr 15 15 ns /ras precharge to /cas hold time t rpc 5 5 ns access time from /cas precharge t cpa 35 40 ns fast page mode cycle time t pc 4 0 45 ns /cas precharge time (fast page) t cp 10 10 ns /ras pulse width (fast page ) t rasp 60 100k 70 100k ns /w to /ras precharge time (c - b - r refresh) t wrp 10 10 ns /w to /ras hold time (c - b - r refresh) t wrh 10 10 ns /cas precharge(c - b - r counter test) t cpt 20 30 ns notes 1. an initial pause of 200 m s is required after power - up followed by any 8 /ras - only or /cas - before - /ras refresh cycles before proper device operation is achieved. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih(min) and v il(max) and are assumed to be 5ns for all inputs. 3. measured with a load equivalent to 1ttl loads and 100pf 4. operation within the t rcd(max) limit insures that t rac(max) can be met. t rcd(max ) is specified as a reference point only. if t rcd is greater than the specified t rcd(max) limit, then access time is controlled exclusively by t cac . 5. assumes that t rcd 3 t rcd(max)
hanbit hm d16m32m8g url: www.hbe.co.kr hanbit electronics co.,ltd. rev. 1.0 (august. 2002) 6 6. t ar , t wcr , t dhr are referenced to t rad(max) 7.this parameter defines the t ime at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 8. t wcs , t rwd , t cwd and t awd are non restrictive operating parameter. they are included in the data sheet as electrical characteristic only. if t wcs 3 tw cs(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. either t rch or t rrh must be satisfied for a read cycle. 10. these parameters are referenced to the /cas leading edge in early w rite cycles and to the /w leading edge in read - write cycles. 11. operation within the t rad(max) limit insures that t rac(max) can be met. t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit. then a ccess time is controlled by t aa . timing diagrams timing waveform of read cycle
hanbit hm d16m32m8g url: www.hbe.co.kr hanbit electronics co.,ltd. rev. 1.0 (august. 2002) 7 timing waveform of write cycle (early write)
hanbit hm d16m32m8g url: www.hbe.co.kr hanbit electronics co.,ltd. rev. 1.0 (august. 2002) 8 write cycle (/oe controlled write) note: dout=open
hanbit hm d16m32m8g url: www.hbe.co.kr hanbit electronics co.,ltd. rev. 1.0 (august. 2002) 9 /cas - before - /ras refresh counter test cycl e
hanbit hm d16m32m8g url: www.hbe.co.kr hanbit electronics co.,ltd. rev. 1.0 (august. 2002) 10 0.25mm min 2.54 mm 1.27 gold : 1.04 0. 10 mm solder:0.914 0.10mm packaging informatio n simm design o r dering information part number density org. package component number vcc mode speed HMD16M32M8G - 5 64byte x 32 72 pin - simm 8ea 5v fpm 50ns HMD16M32M8G - 6 64byte x 32 72 pin - simm 8ea 5v fpm 60ns 1.2 7 10% 3.34 mm 1 107.95 mm 2.03 1.02 mm 6.35 mm 1.27 mm 95.25 mm 6.35 3.18 mm d ia 0.51 mm 101.19 3.38 mm r 1.57 mm 20.00 mm 6.35 mm 10.16 mm 72
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